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Up to four cores side by side: maturity, license, tests and activity.

AttributeLiteDRAMwb_ramfifo
MaturityM2 · Simulation-testedM1 · PrototypeM2 · Simulation-tested
LicenseNo license foundNo license foundNo license found
LanguageMigen/Python/Verilog——
Testsyes—yes
CIyes——
Formal———
FuseSoC——yes
Activityupdated 1 day ago—updated 6 years ago
Boards———
InterfacesMemoryMemory, WishboneFIFO/stream, Memory
CategoryMemory and storageMemory and storageMemory and storage

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