Compare cores
Up to four cores side by side: maturity, license, tests and activity.
| Attribute | LiteEth | LiteSPI | verilog-ethernet | uart verilog by alexforencich |
|---|---|---|---|---|
| Maturity | M2 · Simulation-tested | M2 · Simulation-tested | M2 · Simulation-tested | M2 · Simulation-tested |
| License | No license found | BSD-2-Clause · Commercial-friendly | MIT · Commercial-friendly | MIT · Commercial-friendly |
| Language | Migen/Python/Verilog | Migen/Python/Verilog | — | — |
| Tests | yes | yes | yes | yes |
| CI | yes | yes | yes | yes |
| Formal | — | — | — | — |
| FuseSoC | — | — | — | — |
| Activity | updated 4 days ago | updated 13 days ago | updated 2 years ago | updated 2 years ago |
| Boards | — | — | — | — |
| Interfaces | Ethernet | SPI/QSPI | Ethernet | UART |
| Category | Interfaces and peripherals | Interfaces and peripherals | Interfaces and peripherals | Interfaces and peripherals |