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Up to four cores side by side: maturity, license, tests and activity.

AttributeLiteHyperBusfifoLiteDRAM
MaturityM1 · PrototypeM2 · Simulation-testedM2 · Simulation-tested
LicenseNo license foundNo license foundNo license found
Language——Migen/Python/Verilog
Tests—yesyes
CI——yes
Formal———
FuseSoC—yes—
Activity—updated 6 years agoupdated 1 day ago
Boards———
InterfacesMemoryFIFO/stream, MemoryMemory
CategoryMemory and storageMemory and storageMemory and storage

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