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Up to four cores side by side: maturity, license, tests and activity.

AttributeLiteSATAwb_ram
MaturityM2 · Simulation-testedM1 · Prototype
LicenseNo license foundNo license found
LanguageMigen/Python/Verilog—
Testsyes—
CIyes—
Formal——
FuseSoC——
Activityupdated 9 days ago—
Boards——
InterfacesSATAMemory, Wishbone
CategoryMemory and storageMemory and storage

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