Compare cores
Up to four cores side by side: maturity, license, tests and activity.
| Attribute | opencores cordic | OpenCores WDSP |
|---|---|---|
| Maturity | M1 · Prototype | M1 · Prototype |
| License | No license found | LGPL · Copyleft |
| Language | Verilog/VHDL unknown until review | VHDL |
| Tests | — | — |
| CI | — | — |
| Formal | — | — |
| FuseSoC | — | — |
| Activity | — | — |
| Boards | — | — |
| Interfaces | — | Wishbone |
| Category | DSP and radio | DSP and radio |