The source appears stale or legacy.
OpenCores WDSP
Example of DSP cores with Wishbone and claimed FPGA evidence.
DSP and radioVHDLLGPLM1 · Prototype
Worth knowing
Facts
The source is not on GitHub — an editor checks tests and license manually.
- Maturity
- M1 · Prototype
- License
- LGPL · Copyleft
- Tests
- not found
- CI
- not found
- Formal verification
- not found
- FuseSoC
- not found
Source exists, but no tests were found. How maturity is assigned
Purpose
WishboneGHDL
Boards
No one has confirmed a board run yet.
Add evidenceSources
- OpenCores WDSP source · 2026-04-30
How to check it locally
- Try a synthesis smoke run with: GHDL.
Scores and how they are computed
License, tests, CI, formal checks, documentation and activity come from the repository check. Usefulness and learning value are editorial estimates.
Quality36
Verification15
License55
Docs35
Integration45
Usefulness54
Beginner42
Professional26
Confidence20
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