Compare cores
Up to four cores side by side: maturity, license, tests and activity.
| Attribute | opencores ddr controller | fifo | wb_ram | LiteDRAM |
|---|---|---|---|---|
| Maturity | M1 · Prototype | M2 · Simulation-tested | M1 · Prototype | M2 · Simulation-tested |
| License | No license found | No license found | No license found | No license found |
| Language | Verilog/VHDL unknown until review | — | — | Migen/Python/Verilog |
| Tests | — | yes | — | yes |
| CI | — | — | — | yes |
| Formal | — | — | — | — |
| FuseSoC | — | yes | — | — |
| Activity | — | updated 6 years ago | — | updated 1 day ago |
| Boards | — | — | — | — |
| Interfaces | Memory | FIFO/stream, Memory | Memory, Wishbone | Memory |
| Category | Memory and storage | Memory and storage | Memory and storage | Memory and storage |