Compare cores
Up to four cores side by side: maturity, license, tests and activity.
| Attribute | opencores gpio | wb_intercon | verilog-axis | verilog-axi |
|---|---|---|---|---|
| Maturity | M1 · Prototype | M2 · Simulation-tested | M2 · Simulation-tested | M2 · Simulation-tested |
| License | No license found | ISC · Commercial-friendly | MIT · Commercial-friendly | MIT · Commercial-friendly |
| Language | Verilog/VHDL unknown until review | — | — | — |
| Tests | — | yes | yes | yes |
| CI | — | — | yes | yes |
| Formal | — | — | — | — |
| FuseSoC | — | yes | — | — |
| Activity | — | updated 8 months ago | updated 2 years ago | updated 2 years ago |
| Boards | — | — | — | — |
| Interfaces | GPIO | Wishbone | FIFO/stream, AXI | AXI |
| Category | Buses and infrastructure | Buses and infrastructure | Buses and infrastructure | Buses and infrastructure |