Compare cores
Up to four cores side by side: maturity, license, tests and activity.
| Attribute | opencores minsoc | VexRiscv | NEORV32 | SERV |
|---|---|---|---|---|
| Maturity | M1 · Prototype | M2 · Simulation-tested | M4 · Production-ready | M4 · Production-ready |
| License | No license found | MIT · Commercial-friendly | BSD-3-Clause · Commercial-friendly | ISC · Commercial-friendly |
| Language | Verilog/VHDL unknown until review | SpinalHDL/Scala/Verilog | VHDL | Verilog |
| Tests | — | yes | yes | yes |
| CI | — | yes | yes | yes |
| Formal | — | — | — | — |
| FuseSoC | — | — | — | yes |
| Activity | — | updated 10 days ago | updated 4 days ago | updated 43 days ago |
| Boards | — | — | — | — |
| Interfaces | — | — | — | — |
| Category | CPUs and compute | CPUs and compute | CPUs and compute | CPUs and compute |