Compare cores

Up to four cores side by side: maturity, license, tests and activity.

AttributeOpenRISC or1200VexRiscv
MaturityM2 · Simulation-testedM2 · Simulation-tested
LicenseNo license foundMIT · Commercial-friendly
LanguageVerilogSpinalHDL/Scala/Verilog
Testsyesyes
CI—yes
Formal——
FuseSoC——
Activityupdated 11 years agoupdated 10 days ago
Boards——
Interfaces——
CategoryCPUs and computeCPUs and compute

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