The license requires manual review.
OpenRISC or1200
Historical open soft CPU baseline.
CPUs and computeVerilogNo license foundM2 · Simulation-testedupdated 11 years ago
Worth knowing
Manual review is required.
Facts
From GitHub data, checked October 5, 2026.
- Maturity
- M2 · Simulation-tested
- License
- No license found
- Tests
- yes
- CI
- not found
- Formal verification
- not found
- FuseSoC
- not found
- Last commit
- updated 11 years ago
- Stars
- 183
The repository contains tests or a testbench. How maturity is assigned
Purpose
Verilator
Boards
No one has confirmed a board run yet.
Add evidenceSources
- OpenRISC or1200 source · 2026-04-30
How to check it locally
- Run the upstream simulation/test command from the repository README or CI workflow.
- Try a synthesis smoke run with: Verilator.
Scores and how they are computed
License, tests, CI, formal checks, documentation and activity come from the repository check. Usefulness and learning value are editorial estimates.
Quality40
Verification45
License15
Docs70
Integration35
Usefulness54
Beginner42
Professional43
Confidence40
Similar cores
VexiiRiscv
Checked on GitHubMIT-licensed RISC-V CPU from SpinalHDL, successor of VexRiscv: RV32/64, optional SV32/SV39 MMU, Linux capable, written in SpinalHDL, generates Verilog.
CPUs and computeSpinalHDL (Scala)MITM2 · Simulation-testedupdated 9 days ago
Ibex
Checked on GitHubSmall open RISC-V CPU used by OpenTitan.
CPUs and computeSystemVerilogApache-2.0M2 · Simulation-testedupdated 5 days ago
BlackParrot
Checked on GitHubManycore RISC-V candidate.
CPUs and computeBSD-3-ClauseM2 · Simulation-testedupdated today