Compare cores
Up to four cores side by side: maturity, license, tests and activity.
| Attribute | OpenRISC or1200 | VexRiscv | SERV |
|---|---|---|---|
| Maturity | M2 · Simulation-tested | M2 · Simulation-tested | M4 · Production-ready |
| License | No license found | MIT · Commercial-friendly | ISC · Commercial-friendly |
| Language | Verilog | SpinalHDL/Scala/Verilog | Verilog |
| Tests | yes | yes | yes |
| CI | — | yes | yes |
| Formal | — | — | — |
| FuseSoC | — | — | yes |
| Activity | updated 11 years ago | updated 10 days ago | updated 43 days ago |
| Boards | — | — | — |
| Interfaces | — | — | — |
| Category | CPUs and compute | CPUs and compute | CPUs and compute |