Compare cores
Up to four cores side by side: maturity, license, tests and activity.
| Attribute | pulp-platform common_cells | verilog-axi | verilog-axis |
|---|---|---|---|
| Maturity | M4 · Production-ready | M2 · Simulation-tested | M2 · Simulation-tested |
| License | No license found | MIT · Commercial-friendly | MIT · Commercial-friendly |
| Language | SystemVerilog | — | — |
| Tests | yes | yes | yes |
| CI | yes | yes | yes |
| Formal | yes | — | — |
| FuseSoC | yes | — | — |
| Activity | updated 19 days ago | updated 2 years ago | updated 2 years ago |
| Boards | — | — | — |
| Interfaces | — | AXI | FIFO/stream, AXI |
| Category | Buses and infrastructure | Buses and infrastructure | Buses and infrastructure |