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Up to four cores side by side: maturity, license, tests and activity.

AttributeRocket ChipVexRiscv
MaturityM1 · PrototypeM2 · Simulation-tested
LicenseNo license foundMIT · Commercial-friendly
Language—SpinalHDL/Scala/Verilog
Tests—yes
CIyesyes
Formalyes—
FuseSoC——
Activityupdated 25 days agoupdated 10 days ago
Boards——
Interfaces——
CategoryCPUs and computeCPUs and compute

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