Rocket Chip

Important Chisel generator ecosystem.

CPUs and computeNo license foundM1 · Prototypeupdated 24 days ago

Worth knowing

Warning

The license requires manual review.

Facts

From GitHub data, checked October 7, 2026.

Maturity
M1 · Prototype
License
No license found
Tests
not found
CI
yes
Formal verification
yes
FuseSoC
not found
Last commit
updated 24 days ago
Latest release
October 10, 2022
Stars
3880

Source exists, but no tests were found. How maturity is assigned

Boards

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Sources

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Scores and how they are computed

License, tests, CI, formal checks, documentation and activity come from the repository check. Usefulness and learning value are editorial estimates.

Quality58
Verification55
License15
Docs70
Integration35
Usefulness72
Beginner42
Professional57
Confidence40

Similar cores

VexiiRiscv

Checked on GitHub

MIT-licensed RISC-V CPU from SpinalHDL, successor of VexRiscv: RV32/64, optional SV32/SV39 MMU, Linux capable, written in SpinalHDL, generates Verilog.

CPUs and computeSpinalHDL (Scala)MITM2 · Simulation-testedupdated 9 days ago