Compare cores
Up to four cores side by side: maturity, license, tests and activity.
| Attribute | ultraembedded core_soc | SERV | NEORV32 | VexiiRiscv |
|---|---|---|---|---|
| Maturity | M1 · Prototype | M4 · Production-ready | M4 · Production-ready | M2 · Simulation-tested |
| License | GPL-2.0 · Copyleft | ISC · Commercial-friendly | BSD-3-Clause · Commercial-friendly | MIT · Commercial-friendly |
| Language | — | Verilog | VHDL | SpinalHDL (Scala) |
| Tests | — | yes | yes | yes |
| CI | — | yes | yes | yes |
| Formal | — | — | — | — |
| FuseSoC | — | yes | — | — |
| Activity | updated 6 years ago | updated 43 days ago | updated 3 days ago | updated 1 day ago |
| Boards | — | — | — | — |
| Interfaces | — | — | — | AXI4, Wishbone, Tilelink, AXI4, Wishbone, Tilelink |
| Category | CPUs and compute | CPUs and compute | CPUs and compute | CPUs and compute |