SoC integration candidate.
CPUs and computeGPL-2.0M1 · Prototypeupdated 6 years ago
From GitHub data, checked October 7, 2026.
Source exists, but no tests were found. How maturity is assigned
No one has confirmed a board run yet.
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License, tests, CI, formal checks, documentation and activity come from the repository check. Usefulness and learning value are editorial estimates.
MIT-licensed RISC-V CPU from SpinalHDL, successor of VexRiscv: RV32/64, optional SV32/SV39 MMU, Linux capable, written in SpinalHDL, generates Verilog.
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Small open RISC-V CPU used by OpenTitan.
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Manycore RISC-V candidate.
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