Compare cores
Up to four cores side by side: maturity, license, tests and activity.
| Attribute | ultraembedded core_soc | SERV | VexiiRiscv | VexRiscv |
|---|---|---|---|---|
| Maturity | M1 · Prototype | M4 · Production-ready | M2 · Simulation-tested | M2 · Simulation-tested |
| License | GPL-2.0 · Copyleft | ISC · Commercial-friendly | MIT · Commercial-friendly | MIT · Commercial-friendly |
| Language | — | Verilog | SpinalHDL (Scala) | SpinalHDL/Scala/Verilog |
| Tests | — | yes | yes | yes |
| CI | — | yes | yes | yes |
| Formal | — | — | — | — |
| FuseSoC | — | yes | — | — |
| Activity | updated 6 years ago | updated 43 days ago | updated 1 day ago | updated 10 days ago |
| Boards | — | — | — | — |
| Interfaces | — | — | AXI4, Wishbone, Tilelink, AXI4, Wishbone, Tilelink | — |
| Category | CPUs and compute | CPUs and compute | CPUs and compute | CPUs and compute |