Compare cores
Up to four cores side by side: maturity, license, tests and activity.
| Attribute | ultraembedded core_soc | VexiiRiscv |
|---|---|---|
| Maturity | M1 · Prototype | M2 · Simulation-tested |
| License | GPL-2.0 · Copyleft | MIT · Commercial-friendly |
| Language | — | SpinalHDL (Scala) |
| Tests | — | yes |
| CI | — | yes |
| Formal | — | — |
| FuseSoC | — | — |
| Activity | updated 6 years ago | updated 9 days ago |
| Boards | — | — |
| Interfaces | — | AXI4, Wishbone, Tilelink, AXI4, Wishbone, Tilelink |
| Category | CPUs and compute | CPUs and compute |