Compare cores

Up to four cores side by side: maturity, license, tests and activity.

Attributeverilog-pcieverilog-ethernetuart verilog by alexforencich
MaturityM2 · Simulation-testedM2 · Simulation-testedM2 · Simulation-tested
LicenseMIT · Commercial-friendlyMIT · Commercial-friendlyMIT · Commercial-friendly
Language———
Testsyesyesyes
CIyesyesyes
Formal———
FuseSoC———
Activityupdated 2 years agoupdated 2 years agoupdated 2 years ago
Boards———
InterfacesPCIeEthernetUART
CategoryInterfaces and peripheralsInterfaces and peripheralsInterfaces and peripherals

From the same category