Compare cores

Up to four cores side by side: maturity, license, tests and activity.

Attributewb_ramLiteDRAMLiteSDCardfifo
MaturityM1 · PrototypeM2 · Simulation-testedM2 · Simulation-testedM2 · Simulation-tested
LicenseNo license foundNo license foundNo license foundNo license found
Language—Migen/Python/VerilogMigen/Python/Verilog—
Tests—yesyesyes
CI—yesyes—
Formal————
FuseSoC———yes
Activity—updated 1 day agoupdated 1 day agoupdated 6 years ago
Boards————
InterfacesMemory, WishboneMemorySD/SDIOFIFO/stream, Memory
CategoryMemory and storageMemory and storageMemory and storageMemory and storage