Compare cores
Up to four cores side by side: maturity, license, tests and activity.
| Attribute | ZipCPU wb2axip | verilog-axis | wb_intercon | taxi |
|---|---|---|---|---|
| Maturity | M2 · Simulation-tested | M2 · Simulation-tested | M2 · Simulation-tested | M2 · Simulation-tested |
| License | No license found | MIT · Commercial-friendly | ISC · Commercial-friendly | CERN-OHL-S-2.0 · Copyleft |
| Language | Verilog | — | — | — |
| Tests | yes | yes | yes | yes |
| CI | — | yes | — | yes |
| Formal | yes | — | — | — |
| FuseSoC | yes | — | yes | — |
| Activity | updated 26 days ago | updated 2 years ago | updated 8 months ago | updated 40 days ago |
| Boards | — | — | — | — |
| Interfaces | Wishbone, AXI | FIFO/stream, AXI | Wishbone | FIFO/stream, AXI |
| Category | Buses and infrastructure | Buses and infrastructure | Buses and infrastructure | Buses and infrastructure |