LiteDRAM
Checked on GitHubOpen DRAM controller ecosystem used with LiteX.
Memory and storageMigen/Python/VerilogNo license foundM2 · Simulation-testedupdated 7 days ago
IObundle cache
Open cache candidate.
Memory and storageCERN-OHL-S-2.0M1 · Prototypeupdated 16 days ago
Facts
From GitHub data, checked October 5, 2026.
- Maturity
- M1 · Prototype
- License
- CERN-OHL-S-2.0 · Copyleft
- Tests
- not found
- CI
- yes
- Formal verification
- not found
- FuseSoC
- not found
- Last commit
- updated 16 days ago
- Latest release
- December 3, 2025
- Stars
- 197
Source exists, but no tests were found. How maturity is assigned
Purpose
Memory
Boards
No one has confirmed a board run yet.
Add evidenceSources
- IObundle cache source · 2026-04-30
How to check it locally
No reproducible command known. Help add one.
Scores and how they are computed
License, tests, CI, formal checks, documentation and activity come from the repository check. Usefulness and learning value are editorial estimates.
Quality63
Verification35
License55
Docs70
Integration35
Usefulness54
Beginner42
Professional49
Confidence40
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