Cores
Open HDL cores for FPGA. License, tests and activity checked on GitHub.
| Core | Maturity | License | Language | Activity |
|---|---|---|---|---|
| VexiiRiscv CPUs and compute | M2 · Simulation-tested | MIT | SpinalHDL (Scala) | updated 9 days ago |
| Efinix Sapphire RV64 SoC CPUs and compute | M1 · Prototype | No license found | — | — |