Cores
Open HDL cores for FPGA. License, tests and activity checked on GitHub.
| Core | Maturity | License | Language | Activity |
|---|---|---|---|---|
| VexiiRiscv CPUs and compute | M2 · Simulation-tested | MIT | SpinalHDL (Scala) | updated 9 days ago |
| Caliptra RTL Cryptography | M4 · Production-ready | Apache-2.0 | — | updated 1 day ago |
| OpenTitan KMAC IP Cryptography | M4 · Production-ready | Apache-2.0 | — | updated 1 day ago |
| OpenTitan prim library Buses and infrastructure | M4 · Production-ready | Apache-2.0 | — | updated 1 day ago |
| Ibex CPUs and compute | M2 · Simulation-tested | Apache-2.0 | SystemVerilog | updated 5 days ago |
| OpenTitan IP blocks Cryptography | M4 · Production-ready | Apache-2.0 | SystemVerilog | updated 2 days ago |
| BlackParrot CPUs and compute | M2 · Simulation-tested | BSD-3-Clause | — | updated today |
| SERV CPUs and compute | M4 · Production-ready | ISC | Verilog | updated 43 days ago |
| OpenTitan UART IP Interfaces and peripherals | M4 · Production-ready | Apache-2.0 | — | updated 1 day ago |
| OpenTitan AES IP Cryptography | M4 · Production-ready | Apache-2.0 | — | updated 1 day ago |
| OpenTitan HMAC IP Cryptography | M4 · Production-ready | Apache-2.0 | — | updated 1 day ago |
| OpenTitan I2C IP Interfaces and peripherals | M4 · Production-ready | Apache-2.0 | — | updated 1 day ago |
| OpenTitan SPI device IP Interfaces and peripherals | M4 · Production-ready | Apache-2.0 | — | updated 1 day ago |
| uart verilog by alexforencich Interfaces and peripherals | M2 · Simulation-tested | MIT | — | updated 2 years ago |
| Amaranth HDL Generators and frameworks | M4 · Production-ready | BSD-2-Clause | — | updated 19 days ago |
| LiteSPI Interfaces and peripherals | M2 · Simulation-tested | BSD-2-Clause | Migen/Python/Verilog | updated 13 days ago |
| NEORV32 CPUs and compute | M4 · Production-ready | BSD-3-Clause | VHDL | updated 3 days ago |
| VexRiscv CPUs and compute | M2 · Simulation-tested | MIT | SpinalHDL/Scala/Verilog | updated 10 days ago |
| wb_intercon Buses and infrastructure | M2 · Simulation-tested | ISC | — | updated 8 months ago |
| verilog-axi Buses and infrastructure | M2 · Simulation-tested | MIT | — | updated 2 years ago |
| verilog-axis Buses and infrastructure | M2 · Simulation-tested | MIT | — | updated 2 years ago |
| verilog-ethernet Interfaces and peripherals | M2 · Simulation-tested | MIT | — | updated 2 years ago |
| stream_utils Buses and infrastructure | M2 · Simulation-tested | ISC | — | updated 12 months ago |
| PicoRV32 CPUs and compute | M2 · Simulation-tested | ISC | Verilog | updated 30 days ago |