Cores
Open HDL cores for FPGA. License, tests and activity checked on GitHub.
| Core | Maturity | License | Language | Activity |
|---|---|---|---|---|
| SERV CPUs and compute | M4 · Production-ready | ISC | Verilog | updated 43 days ago |
Submit a core
Open HDL cores for FPGA. License, tests and activity checked on GitHub.
| Core | Maturity | License | Language | Activity |
|---|---|---|---|---|
| SERV CPUs and compute | M4 · Production-ready | ISC | Verilog | updated 43 days ago |