Commercial PCIe DMA IP between FPGA and host with kernel-bypass Linux driver; encrypted RTL, commercial license.
Interfaces and peripheralsVerilogCustom licenseM1 · Prototype
Cores
Open HDL cores for FPGA. License, tests and activity checked on GitHub.
Commercial 10G TCP/IP and UDP/IP offload engine IP (L2-L4) with AXI-4 Stream interfaces; encrypted RTL, commercial license.
Interfaces and peripheralsVerilogCustom licenseM1 · Prototype
Commercial Ethernet MAC/PCS IP for 1G to 100G with optional RS-FEC at 25G and 100G; encrypted RTL, commercial license.
Interfaces and peripheralsVerilogCustom licenseM1 · Prototype