Cores

AXI component library and comparison source.

Buses and infrastructureMITM2 · Simulation-testedupdated 2 years ago

AXI-Stream component library.

Buses and infrastructureMITM2 · Simulation-testedupdated 2 years ago

Successor ecosystem for AXI/stream components.

Buses and infrastructureCERN-OHL-S-2.0M2 · Simulation-testedupdated 40 days ago

Wishbone/AXI bridge and formal property library.

Buses and infrastructureVerilogNo license foundM2 · Simulation-testedupdated 26 days ago

FuseSoC-listed open logic package family.

Buses and infrastructureNo license foundM4 · Production-readyupdated 6 days ago

AXI components and infrastructure.

Buses and infrastructureSystemVerilogNo license foundM4 · Production-readyupdated 13 days ago

MIT-licensed RISC-V CPU from SpinalHDL, successor of VexRiscv: RV32/64, optional SV32/SV39 MMU, Linux capable, written in SpinalHDL, generates Verilog.

CPUs and computeSpinalHDL (Scala)MITM2 · Simulation-testedupdated 9 days ago

CERN's library of common RTL components in VHDL-2008: memories, I/O, clock domain crossing, stream interfaces. Licence CERN-OHL-W-2.0.

Buses and infrastructureVHDL-2008CERN-OHL-W-2.0M1 · Prototype

Commercial PCIe DMA IP between FPGA and host with kernel-bypass Linux driver; encrypted RTL, commercial license.

Interfaces and peripheralsVerilogCustom licenseM1 · Prototype

Commercial 10G TCP/IP and UDP/IP offload engine IP (L2-L4) with AXI-4 Stream interfaces; encrypted RTL, commercial license.

Interfaces and peripheralsVerilogCustom licenseM1 · Prototype

Commercial Ethernet MAC/PCS IP for 1G to 100G with optional RS-FEC at 25G and 100G; encrypted RTL, commercial license.

Interfaces and peripheralsVerilogCustom licenseM1 · Prototype

Configurable soft RISC-V SoC from Efinix: 1 to 4 64-bit cores, optional SV39 MMU, L1 and L2 caches, DDR3, LPDDR4x and HyperRAM controller for Efinix FPGAs; licence not stated.

CPUs and computeNo license foundM1 · Prototype