Cores
Open HDL cores for FPGA. License, tests and activity checked on GitHub.
| Core | Maturity | License | Language | Activity |
|---|---|---|---|---|
| Orthogone ULL PCIe circular-buffer DMA controller (Gen3/Gen4) Interfaces and peripherals | M1 · Prototype | Commercial license; encrypted RTL (closed source) | Verilog | — |
| Orthogone ULL 10G TCP/IP and UDP/IP Offload Engine Interfaces and peripherals | M1 · Prototype | Commercial license; encrypted RTL (closed source) | Verilog | — |
| Orthogone ULL Ethernet MAC/PCS 1G-100G with optional RS-FEC Interfaces and peripherals | M1 · Prototype | Commercial license; encrypted RTL (closed source) | Verilog | — |