Compare boards
Up to four boards side by side: chip, logic, toolchains, interfaces and price.
| Attribute | DE10-Nano | Tang Nano 20K | Arty A7 | MicroZed |
|---|---|---|---|---|
| FPGA | 5CSEBA6U23I7 | GW2AR-LV18QN88C8/I7 | XC7A35TICSG324-1L | XC7Z010-1CLG400C |
| Family | Cyclone V SoC | GW2AR | Artix-7 | Zynq-7000 |
| Logic (LUTs) | not listed | 20736 | not listed | not listed |
| Price | at the seller | 28.17 USD | at the seller | at the seller |
| Open toolchain | Mistral | Project Apicula | Project X-Ray / openXC7 | Project X-Ray / openXC7 |
| Toolchains | Intel Quartus Prime | Gowin EDA, Yosys + nextpnr-gowin + Apicula | Vivado WebPACK / ML Standard | AMD Vivado, Project X-Ray / openXC7 |
| Interfaces | HDMI TX, Ethernet, USB | HDMI, MAX98357A I2S amplifier path, TF card slot, USB Type-C, Onboard BL616 JTAG, USB UART | Ethernet, USB UART, USB-JTAG | Ethernet |
| Memory | HPS DDR3 requires Terasic manual verification | 32-bit SDR SDRAM 64 Mbit, Onboard flash 64 Mbit | DDR3 variant-specific; verify in Digilent memory tab | not listed |
| Level | Intermediate | Beginner | Beginner | Intermediate |
| Where to get help | Terasic support | Sipeed forum, r/GowinFPGA | Digilent Forum | official docs |
| Known issues | — | Onboard debugger recognition; Flash persistence mode | 35T and 100T variants differ | — |