Compare cores

Up to four cores side by side: maturity, license, tests and activity.

AttributeLiteScopeOpenCores WBScopewb_bfm
MaturityM2 · Simulation-testedM1 · PrototypeM2 · Simulation-tested
LicenseNo license foundGPL · CopyleftNo license found
LanguageMigen/Python/VerilogVerilog—
Testsyes—yes
CIyes——
Formal———
FuseSoC——yes
Activityupdated 13 days ago—updated 9 years ago
Boards———
InterfacesJTAG/debugJTAG/debug, WishboneWishbone
CategoryVerification and debugVerification and debugVerification and debug

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