Compare cores

Up to four cores side by side: maturity, license, tests and activity.

Attributeopencores cordicLiteJESD204BOpenCores WDSPopencores fft
MaturityM1 · PrototypeM2 · Simulation-testedM1 · PrototypeM1 · Prototype
LicenseNo license foundNo license foundLGPL · CopyleftNo license found
LanguageVerilog/VHDL unknown until review—VHDLVerilog/VHDL unknown until review
Tests—yes——
CI—yes——
Formal————
FuseSoC————
Activity—updated 13 days ago——
Boards————
Interfaces——Wishbone—
CategoryDSP and radioDSP and radioDSP and radioDSP and radio