Compare cores

Up to four cores side by side: maturity, license, tests and activity.

Attributeopencores cordicOpenCores WDSPopencores fftLiteJESD204B
MaturityM1 · PrototypeM1 · PrototypeM1 · PrototypeM2 · Simulation-tested
LicenseNo license foundLGPL · CopyleftNo license foundNo license found
LanguageVerilog/VHDL unknown until reviewVHDLVerilog/VHDL unknown until review—
Tests———yes
CI———yes
Formal————
FuseSoC————
Activity———updated 13 days ago
Boards————
Interfaces—Wishbone——
CategoryDSP and radioDSP and radioDSP and radioDSP and radio