Compare cores
Up to four cores side by side: maturity, license, tests and activity.
| Attribute | opencores ddr controller | IObundle cache | wb_ram | LiteSATA |
|---|---|---|---|---|
| Maturity | M1 · Prototype | M1 · Prototype | M1 · Prototype | M2 · Simulation-tested |
| License | No license found | CERN-OHL-S-2.0 · Copyleft | No license found | No license found |
| Language | Verilog/VHDL unknown until review | — | — | Migen/Python/Verilog |
| Tests | — | — | — | yes |
| CI | — | yes | — | yes |
| Formal | — | — | — | — |
| FuseSoC | — | — | — | — |
| Activity | — | updated 16 days ago | — | updated 9 days ago |
| Boards | — | — | — | — |
| Interfaces | Memory | Memory | Memory, Wishbone | SATA |
| Category | Memory and storage | Memory and storage | Memory and storage | Memory and storage |