Compare cores

Up to four cores side by side: maturity, license, tests and activity.

Attributeopencores fftopencores cordicOpenCores WDSPLiteJESD204B
MaturityM1 · PrototypeM1 · PrototypeM1 · PrototypeM2 · Simulation-tested
LicenseNo license foundNo license foundLGPL · CopyleftNo license found
LanguageVerilog/VHDL unknown until reviewVerilog/VHDL unknown until reviewVHDL—
Tests———yes
CI———yes
Formal————
FuseSoC————
Activity———updated 13 days ago
Boards————
Interfaces——Wishbone—
CategoryDSP and radioDSP and radioDSP and radioDSP and radio