Compare cores
Up to four cores side by side: maturity, license, tests and activity.
| Attribute | opencores minsoc | VexRiscv | Ibex | VexiiRiscv |
|---|---|---|---|---|
| Maturity | M1 · Prototype | M2 · Simulation-tested | M2 · Simulation-tested | M2 · Simulation-tested |
| License | No license found | MIT · Commercial-friendly | Apache-2.0 · Commercial-friendly | MIT · Commercial-friendly |
| Language | Verilog/VHDL unknown until review | SpinalHDL/Scala/Verilog | SystemVerilog | SpinalHDL (Scala) |
| Tests | — | yes | yes | yes |
| CI | — | yes | yes | yes |
| Formal | — | — | yes | — |
| FuseSoC | — | — | yes | — |
| Activity | — | updated 10 days ago | updated 2 days ago | updated 1 day ago |
| Boards | — | — | — | — |
| Interfaces | — | — | — | AXI4, Wishbone, Tilelink, AXI4, Wishbone, Tilelink |
| Category | CPUs and compute | CPUs and compute | CPUs and compute | CPUs and compute |