Compare cores
Up to four cores side by side: maturity, license, tests and activity.
| Attribute | OpenCores UART16550 | verilog-ethernet | LiteSPI | OpenTitan UART IP |
|---|---|---|---|---|
| Maturity | M1 · Prototype | M2 · Simulation-tested | M2 · Simulation-tested | M4 · Production-ready |
| License | No license found | MIT · Commercial-friendly | BSD-2-Clause · Commercial-friendly | Apache-2.0 · Commercial-friendly |
| Language | Verilog | — | Migen/Python/Verilog | — |
| Tests | — | yes | yes | yes |
| CI | — | yes | yes | yes |
| Formal | — | — | — | — |
| FuseSoC | — | — | — | yes |
| Activity | — | updated 2 years ago | updated 14 days ago | updated 1 day ago |
| Boards | — | — | — | — |
| Interfaces | UART | Ethernet | SPI/QSPI | UART |
| Category | Interfaces and peripherals | Interfaces and peripherals | Interfaces and peripherals | Interfaces and peripherals |