Compare cores
Up to four cores side by side: maturity, license, tests and activity.
| Attribute | OpenCores UART16550 | verilog-ethernet | OpenTitan UART IP | LiteSPI |
|---|---|---|---|---|
| Maturity | M1 · Prototype | M2 · Simulation-tested | M4 · Production-ready | M2 · Simulation-tested |
| License | No license found | MIT · Commercial-friendly | Apache-2.0 · Commercial-friendly | BSD-2-Clause · Commercial-friendly |
| Language | Verilog | — | — | Migen/Python/Verilog |
| Tests | — | yes | yes | yes |
| CI | — | yes | yes | yes |
| Formal | — | — | — | — |
| FuseSoC | — | — | yes | — |
| Activity | — | updated 2 years ago | updated 1 day ago | updated 14 days ago |
| Boards | — | — | — | — |
| Interfaces | UART | Ethernet | UART | SPI/QSPI |
| Category | Interfaces and peripherals | Interfaces and peripherals | Interfaces and peripherals | Interfaces and peripherals |