Compare cores

Up to four cores side by side: maturity, license, tests and activity.

AttributeOpenCores WBScopeLiteScopewb_bfm
MaturityM1 · PrototypeM2 · Simulation-testedM2 · Simulation-tested
LicenseGPL · CopyleftNo license foundNo license found
LanguageVerilogMigen/Python/Verilog—
Tests—yesyes
CI—yes—
Formal———
FuseSoC——yes
Activity—updated 13 days agoupdated 9 years ago
Boards———
InterfacesJTAG/debug, WishboneJTAG/debugWishbone
CategoryVerification and debugVerification and debugVerification and debug

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