Compare cores

Up to four cores side by side: maturity, license, tests and activity.

AttributeOpenCores WDSPLiteJESD204Bopencores fftopencores cordic
MaturityM1 · PrototypeM2 · Simulation-testedM1 · PrototypeM1 · Prototype
LicenseLGPL · CopyleftNo license foundNo license foundNo license found
LanguageVHDL—Verilog/VHDL unknown until reviewVerilog/VHDL unknown until review
Tests—yes——
CI—yes——
Formal————
FuseSoC————
Activity—updated 13 days ago——
Boards————
InterfacesWishbone———
CategoryDSP and radioDSP and radioDSP and radioDSP and radio