Compare cores

Up to four cores side by side: maturity, license, tests and activity.

AttributeRocket ChipVexiiRiscvIbex
MaturityM1 · PrototypeM2 · Simulation-testedM2 · Simulation-tested
LicenseNo license foundMIT · Commercial-friendlyApache-2.0 · Commercial-friendly
Language—SpinalHDL (Scala)SystemVerilog
Tests—yesyes
CIyesyesyes
Formalyes—yes
FuseSoC——yes
Activityupdated 25 days agoupdated 1 day agoupdated 1 day ago
Boards———
Interfaces—AXI4, Wishbone, Tilelink, AXI4, Wishbone, Tilelink—
CategoryCPUs and computeCPUs and computeCPUs and compute

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