CORE-V-VERIF

Verification evidence model for CORE-V cores.

Verification and debugSystemVerilog/UVMNo license foundM4 · Production-readyupdated 23 days ago

Worth knowing

Warning

The license requires manual review.

Facts

From GitHub data, checked October 6, 2026.

Maturity
M4 · Production-ready
License
No license found
Tests
yes
CI
yes
Formal verification
yes
FuseSoC
not found
Last commit
updated 23 days ago
Latest release
July 11, 2024
Stars
727

Tests, CI, releases and active development within the last year. How maturity is assigned

Purpose

Verilator

Boards

No one has confirmed a board run yet.

Add evidence

Sources

How to check it locally
  • Run the upstream simulation/test command from the repository README or CI workflow.
  • Try a synthesis smoke run with: Verilator.
Scores and how they are computed

License, tests, CI, formal checks, documentation and activity come from the repository check. Usefulness and learning value are editorial estimates.

Quality65
Verification85
License15
Docs70
Integration35
Usefulness72
Beginner42
Professional75
Confidence40

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