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OpenHW CORE-V cores
Open RISC-V processor cores.
CPUs and computeSystemVerilogSolderpadM1 · Prototypeupdated 6 months ago
Worth knowing
Facts
From GitHub data, checked October 6, 2026.
- Maturity
- M1 · Prototype
- License
- Solderpad · Commercial-friendly
- Tests
- not found
- CI
- not found
- Formal verification
- not found
- FuseSoC
- not found
- Last commit
- updated 6 months ago
- Stars
- 374
Source exists, but no tests were found. How maturity is assigned
Purpose
Verilator
Boards
No one has confirmed a board run yet.
Add evidenceSources
- OpenHW CORE-V cores source · 2026-04-30
How to check it locally
- Try a synthesis smoke run with: Verilator.
Scores and how they are computed
License, tests, CI, formal checks, documentation and activity come from the repository check. Usefulness and learning value are editorial estimates.
Quality66
Verification15
License90
Docs70
Integration35
Usefulness72
Beginner42
Professional41
Confidence40
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