The license requires manual review.
OpenHW CVA6
Linux-capable RISC-V core lineage.
CPUs and computeSystemVerilogNo license foundM4 · Production-readyupdated 3 days ago
Worth knowing
Facts
From GitHub data, checked October 5, 2026.
- Maturity
- M4 · Production-ready
- License
- No license found
- Tests
- yes
- CI
- yes
- Formal verification
- yes
- FuseSoC
- yes
- Last commit
- updated 3 days ago
- Latest release
- February 3, 2025
- Stars
- 3145
Tests, CI, releases and active development within the last year. How maturity is assigned
Purpose
Verilator
Boards
No one has confirmed a board run yet.
Add evidenceSources
- OpenHW CVA6 source · 2026-04-30
How to check it locally
- Run the upstream simulation/test command from the repository README or CI workflow.
- Inspect the upstream FuseSoC .core manifest and use it as the integration entrypoint.
- Try a synthesis smoke run with: Verilator.
Scores and how they are computed
License, tests, CI, formal checks, documentation and activity come from the repository check. Usefulness and learning value are editorial estimates.
Quality65
Verification85
License15
Docs70
Integration55
Usefulness72
Beginner42
Professional75
Confidence40
Similar cores
VexiiRiscv
Checked on GitHubMIT-licensed RISC-V CPU from SpinalHDL, successor of VexRiscv: RV32/64, optional SV32/SV39 MMU, Linux capable, written in SpinalHDL, generates Verilog.
CPUs and computeSpinalHDL (Scala)MITM2 · Simulation-testedupdated 9 days ago
Ibex
Checked on GitHubSmall open RISC-V CPU used by OpenTitan.
CPUs and computeSystemVerilogApache-2.0M2 · Simulation-testedupdated 5 days ago
BlackParrot
Checked on GitHubManycore RISC-V candidate.
CPUs and computeBSD-3-ClauseM2 · Simulation-testedupdated today