The license requires manual review.
ZipCPU
CPU, Wishbone and formal-heavy ecosystem.
CPUs and computeVerilogNo license foundM2 · Simulation-testedupdated 21 days ago
Worth knowing
Facts
From GitHub data, checked October 5, 2026.
- Maturity
- M2 · Simulation-tested
- License
- No license found
- Tests
- yes
- CI
- not found
- Formal verification
- yes
- FuseSoC
- not found
- Last commit
- updated 21 days ago
- Stars
- 1588
The repository contains tests or a testbench. How maturity is assigned
Purpose
WishboneVerilator
Boards
No one has confirmed a board run yet.
Add evidenceSources
- ZipCPU source · 2026-04-30
How to check it locally
- Run the upstream simulation/test command from the repository README or CI workflow.
- Try a synthesis smoke run with: Verilator.
Scores and how they are computed
License, tests, CI, formal checks, documentation and activity come from the repository check. Usefulness and learning value are editorial estimates.
Quality60
Verification65
License15
Docs70
Integration45
Usefulness72
Beginner42
Professional63
Confidence40
Similar cores
VexiiRiscv
Checked on GitHubMIT-licensed RISC-V CPU from SpinalHDL, successor of VexRiscv: RV32/64, optional SV32/SV39 MMU, Linux capable, written in SpinalHDL, generates Verilog.
CPUs and computeSpinalHDL (Scala)MITM2 · Simulation-testedupdated 9 days ago
Ibex
Checked on GitHubSmall open RISC-V CPU used by OpenTitan.
CPUs and computeSystemVerilogApache-2.0M2 · Simulation-testedupdated 5 days ago
BlackParrot
Checked on GitHubManycore RISC-V candidate.
CPUs and computeBSD-3-ClauseM2 · Simulation-testedupdated today