Historical SoC integration reference.
CPUs and computeVerilog/VHDL unknown until reviewNo license foundM1 · Prototype
Cores
Open HDL cores for FPGA. License, tests and activity checked on GitHub.
Submit a core
Open HDL cores for FPGA. License, tests and activity checked on GitHub.
Historical SoC integration reference.
CPUs and computeVerilog/VHDL unknown until reviewNo license foundM1 · Prototype