Useful Wishbone-accessible debug core by ZipCPU author.
Verification and debugVerilogGPLM1 · Prototype
Cores
Open HDL cores for FPGA. License, tests and activity checked on GitHub.
Example of DSP cores with Wishbone and claimed FPGA evidence.
DSP and radioVHDLLGPLM1 · Prototype
Risk model example for obsolete crypto.
CryptographyVerilog/VHDL unknown until reviewNo license foundM1 · Prototype
Image processing category seed.
Audio and videoVerilog/VHDL unknown until reviewNo license foundM1 · Prototype
Historical hash core.
CryptographyVerilog/VHDL unknown until reviewNo license foundM1 · Prototype
GPIO category seed.
Buses and infrastructureVerilog/VHDL unknown until reviewNo license foundM1 · Prototype
PWM category seed.
Interfaces and peripheralsVerilog/VHDL unknown until reviewNo license foundM1 · Prototype
CORDIC category seed.
DSP and radioVerilog/VHDL unknown until reviewNo license foundM1 · Prototype
FFT category seed.
DSP and radioVerilog/VHDL unknown until reviewNo license foundM1 · Prototype
Small SPI alternative.
Interfaces and peripheralsVerilog/VHDL unknown until reviewNo license foundM1 · Prototype
Canonical UART reference and common FuseSoC adaptations.
Interfaces and peripheralsVerilogNo license foundM1 · Prototype
Important comparison point for LiteEth and IObundle Ethernet.
Interfaces and peripheralsVerilogNo license foundM1 · Prototype
Common small peripheral for beginner/professional comparison.
Interfaces and peripheralsVerilogNo license foundM1 · Prototype
Common reusable peripheral baseline.
Interfaces and peripheralsVerilogNo license foundM1 · Prototype
Historical AES core to compare with OpenTitan AES.
CryptographyVerilog/VHDL unknown until reviewNo license foundM1 · Prototype
CAN/LIN category seed.
Interfaces and peripheralsVerilog/VHDL unknown until reviewNo license foundM1 · Prototype
DDR risk-model example.
Memory and storageVerilog/VHDL unknown until reviewNo license foundM1 · Prototype
Historical SoC integration reference.
CPUs and computeVerilog/VHDL unknown until reviewNo license foundM1 · Prototype
Memory controller comparison.
Memory and storageVerilog/VHDL unknown until reviewNo license foundM1 · Prototype
USB category seed.
Interfaces and peripheralsVerilog/VHDL unknown until reviewNo license foundM1 · Prototype
Video category seed.
Audio and videoVerilog/VHDL unknown until reviewNo license foundM1 · Prototype
IObundle Ethernet
Checked on GitHubEthernet candidate with OpenCores ethmac relation.
Interfaces and peripheralsCERN-OHL-S-2.0M4 · Production-readyupdated 16 days ago
IObundle UART16550
Checked on GitHubModern adaptation of OpenCores UART16550.
Interfaces and peripheralsNo license foundM4 · Production-readyupdated 16 days ago