Cores
Open HDL cores for FPGA. License, tests and activity checked on GitHub.
| Core | Maturity | License | Language | Activity |
|---|---|---|---|---|
| VexiiRiscv CPUs and compute | M2 · Simulation-tested | MIT | SpinalHDL (Scala) | updated 9 days ago |
| OpenRISC mor1kx CPUs and compute | M4 · Production-ready | No license found | Verilog | updated 4 months ago |
| ZipCPU CPUs and compute | M2 · Simulation-tested | No license found | Verilog | updated 21 days ago |