GPIO category seed.
Buses and infrastructureVerilog/VHDL unknown until reviewNo license foundM1 · Prototype
Cores
Open HDL cores for FPGA. License, tests and activity checked on GitHub.
Submit a core
Open HDL cores for FPGA. License, tests and activity checked on GitHub.
GPIO category seed.
Buses and infrastructureVerilog/VHDL unknown until reviewNo license foundM1 · Prototype