Cores

Open HDL cores for FPGA. License, tests and activity checked on GitHub.

3 results

wb_intercon

Checked on GitHub

Common Wishbone interconnect package.

Buses and infrastructureISCM2 · Simulation-testedupdated 8 months ago

CERN's library of common RTL components in VHDL-2008: memories, I/O, clock domain crossing, stream interfaces. Licence CERN-OHL-W-2.0.

Buses and infrastructureVHDL-2008CERN-OHL-W-2.0M1 · Prototype

Checked on GitHub

Wishbone/AXI bridge and formal property library.

Buses and infrastructureVerilogNo license foundM2 · Simulation-testedupdated 26 days ago